I designed and simulated a Pipelined-5-stage MIPS Processor using Verilog on Vivado, incorporating Forwarding and Hazard Detection techniques.
The 5 stages are IF (Instruction Fetch), ID (Instruction Decode), EXE (Execution), MEM (Memory) and WB (Write Back). The pipeline helps to keep all the stages busy at all times. The pipelined datapath is controlled using RTL. There are some situations where hazards happen, so I added the Forwarding units and the required paths to detect the data dependencies and handle data hazards and control hazards. However, there are situations where we cannot avoid delay by forwarding. Then, the pipeline will stall for 1 or more clock cycles, and I added a Hazard Detection unit to detect those situations.
The following two figures show the schematic of the pipelined processor.
